One constraint on the development of new electronic products is the assembly and packaging of the required circuits. Packaging serves multiple functions including to protect the enclosed circuit die surface and to provide a stress release mechanism between the die and the printed circuit board. In addition, the package needs to be compatible with application requirements for small size, high density, and low cost.
In the past, device packages have been assembled as individual units after wafer slicing of the circuit dies. Such packages are several times the size of the enclosed circuit die. More recently, circuit dies have been encapsulated at the wafer level before slicing to produce a significantly smaller package. When a package has an area no more than 1.2 times the enclosed die, it is referred to as a Chip Scale Package (CSP). A Wafer Level CSP extends the wafer fabrication to include device interconnection and device protection processes to produce a package only slightly larger than the enclosed die.
FIG. 1 shows an elevated bottom perspective view of a typical WLCSP 10 according to the prior art. A wafer die 11 contains the device circuitry 12, which is visible through a transparent polymer protective coating that may be present on chip surface. An array of solder ball electrical contacts 13 (also referred to as “bumps”) on the bottom surface of the WLCSP 10 connect the device circuitry 12 within the chip to an external circuit structure such as a circuit board.
As described above, the transparent polymer coating of the WLCSP 10 leaves the underlying device circuitry 12 visually observable to inspection, which may not be desirable. And the light that passes through the transparent polymer coating may adversely affect the operation of the device circuitry 12 within. In addition, the solder ball electrical contacts 13 are relatively fragile and can be damaged during shipping and handling. Similarly, the unencapsulated back side of the WLCSP 10 is susceptible to chipping.